Explore core breakthroughs in SRAM-CIM architecture: hardware-aware compiler and edge-cloud active learning loop
Hardware-Aware AI Model Compiler for SRAM-CIM Architecture
Target Audience: AI Engineers, Embedded System Developers, Academic Researchers
Traditional AI compilers (TVM, MLIR, TensorRT) are designed with von Neumann architecture assumptions and cannot fully leverage CIM's analog-domain computing advantages. CIMCompile is a hardware-aware compiler specifically designed for SRAM-CIM, achieving 2-5x inference performance improvement through a four-layer compilation architecture.
Edge-Cloud Active Learning Loop Mechanism Design
Target Audience: Industrial AI Developers, MLOps Engineers
Static AI models face accuracy degradation in dynamic industrial environments. FlowLoop is an edge-cloud active learning loop that enables continuous model evolution through edge-side confidence evaluation, hard sample filtering, and cloud-based automatic retraining, maintaining accuracy above 95%.
Technical foundations of these whitepapers are based on the following academic research and industry reports
Contact our technical team for complete CIMCompile and FlowLoop whitepapers